1. Field of the Invention
The present invention relates to processors. In one example, the present invention relates to methods and apparatus for processors handling and event such as a fault or reset event.
2. Description of Related Art
Conventional computer systems have processors coupled to system memory. In order to optimize access to data in system memory, individual processors are typically designed to work with cache memory. In one example, each processor has a cache that is loaded with frequently or immediately used instructions and data. Some processors have more than one level of cache. Each cache block can be read or written by the processor.
A processor cache typically includes both instruction cache and data cache. An instruction cache includes operation codes (opcodes) and parameters identifying the operations a processor should perform. Data cache typically includes data values associated with the operations. In some instances, data cache and instruction cache are integrated into a single cache block.
A processor cache also includes state information indicating the state of individual processor cache lines. A processor cache line may be shared, modified, exclusive, owned, or invalid. In some instances, a processor may only be able to distinguish between valid and invalid cache lines. The state information allows a processor to determine when information in cache is stale and a new memory access is needed to obtain new data or instructions.
However, there are some circumstances when the state or data assocaited with each cache line may be inaccurate. For example, a hardware or software fault or a reset event may cause inaccuracies in cache memory. Any event such as a fault or manual reset is referred to herein as a reset event.
Consequently, it is desirable to provide improved methods and apparatus for handling faults and reset events to prevent inaccuracies in processor cache memory.